A Cascaded Nine-Level Inverter Topology With T-Type and H-Bridge With Increased DC-Bus Utilization
Artykuł w czasopiśmie
MNiSW
200
Lista 2021
| Status: | |
| Autorzy: | Pal Souradeep, Majumder Mriganka Ghosh, Resalayyan Rakesh, Gopakumar Kumarukattan Nair, Umanand Loganathan, Zieliński Dariusz, Beig Abdul R. |
| Dyscypliny: | |
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| Rok wydania: | 2021 |
| Wersja dokumentu: | Drukowana | Elektroniczna |
| Język: | angielski |
| Numer czasopisma: | 1 |
| Wolumen/Tom: | 36 |
| Strony: | 285 - 294 |
| Impact Factor: | 5,967 |
| Web of Science® Times Cited: | 27 |
| Scopus® Cytowania: | 39 |
| Bazy: | Web of Science | Scopus |
| Efekt badań statutowych | NIE |
| Materiał konferencyjny: | NIE |
| Publikacja OA: | NIE |
| Abstrakty: | angielski |
| This article introduces a hybrid nine-level inverter topology with extended dc-bus utilization for operation at over modulation range without the presence of lower order harmonics (predominantly fifth and seventh) when compared to conventional two-level and multilevel inverter with hexagonal voltage space vector structure. The proposed inverter is a cascade of a fivelevel T-type unit and an H-bridge (HB) unit. An increase in the dc-bus utilization is possible by increasing the pole voltage levels to ±(V dc /2 + V dc /8) using the HB capacitor voltage and also the capacitor voltages are balanced by adding a offset to sine reference. The aforementioned pulsewidth modulation strategy allows us to increase the peak phase fundamental voltage from 0.577V dc to 0.625V dc in case of unity power factor (p.f) load and to 0.637V dc for 0.82 p.f load with the proposed nine-level inverter. The limiting factor on increasing the dc bus utilization such as p.f, HB capacitor balancing are analysed broadly in this article. The proposed inverter scheme and its claim of increasing the peak phase fundamental voltage is experimentally validated in a laboratory prototype. |
