A Fault Tolerant Inverter Circuit to Generate Thirteen Level 24-sided Voltage Space Vector Structure for Open-end Winding Induction Motor Drive
Artykuł w czasopiśmie
MNiSW
140
Lista 2021
| Status: | |
| Autorzy: | Surana Prashant, Majumder Mriganka Ghosh, Resalayyan Rakesh, Gopakumar Kumarukattan Nair, Umanand Loganathan, Zieliński Dariusz |
| Dyscypliny: | |
| Aby zobaczyć szczegóły należy się zalogować. | |
| Rok wydania: | 2022 |
| Wersja dokumentu: | Drukowana | Elektroniczna |
| Język: | angielski |
| Numer czasopisma: | 6 |
| Wolumen/Tom: | 10 |
| Strony: | 7539 - 7548 |
| Impact Factor: | 5,5 |
| Web of Science® Times Cited: | 0 |
| Scopus® Cytowania: | 6 |
| Bazy: | Web of Science | Scopus |
| Efekt badań statutowych | NIE |
| Materiał konferencyjny: | NIE |
| Publikacja OA: | NIE |
| Abstrakty: | angielski |
| An inverter circuit to generate a thirteen level 24- sided polygonal voltage space vector structure (VSVS) comprised of 288 real active vectors and a zero vector is proposed in this paper. Proposed scheme eliminates lower order harmonics upto 19th order and suppresses higher order harmonics from motor phase voltage in the full modulation range. 48-step operation of the proposed scheme highly improves phase voltage quality at full speed. DC bus utilization of proposed scheme is improved to 99.42% compared to 90.6% multilevel hexagonal VSVS. Proposed topology has inherent capacitor balancing in every sampling interval at any loading condition using pole voltage redundancies. Multilevel property of proposed scheme reduces instantaneous error in phase voltage compared to two-level 24- sided polygonal VSVS. Generation of real active vectors reduces instantaneous error in phase voltage and reduces switching frequency compared switched average techniques existing in literature. Fault tolerant feature of the proposed scheme improves availability of the drive system. Experimental results are provided to validate the steady state operation, capacitor balancing, transient performance and fault tolerant capability of the proposed scheme. The comparison of switching loss and harmonic performance of the proposed scheme is performed with existing topologies. |
