Suppression of Lower Order Harmonics for the Full Modulation Range for a Two-Level Inverter-Fed IM Drive With a Switched-Capacitive Filter Technique Forming a 42-Sided Voltage Space Vector Structure
Artykuł w czasopiśmie
MNiSW
200
Lista 2021
| Status: | |
| Autorzy: | Dewani Rahul, Resalayyan Rakesh, Gopakumar Kumarukattan Nair, Umanand Loganathan, Zieliński Dariusz, Franquelo Leopoldo Garcia |
| Dyscypliny: | |
| Aby zobaczyć szczegóły należy się zalogować. | |
| Rok wydania: | 2022 |
| Wersja dokumentu: | Drukowana | Elektroniczna |
| Język: | angielski |
| Numer czasopisma: | 8 |
| Wolumen/Tom: | 68 |
| Strony: | 6701 - 6709 |
| Web of Science® Times Cited: | 5 |
| Scopus® Cytowania: | 6 |
| Bazy: | Web of Science | Scopus |
| Efekt badań statutowych | NIE |
| Materiał konferencyjny: | NIE |
| Publikacja OA: | NIE |
| Abstrakty: | angielski |
| This article proposes an inverter topology for the first time for suppression of all lower order harmonics (5th, 7th, 11th, 13th, etc.) up to 39th harmonic. The lower order harmonic suppression is achieved by switching the 42-sided polygonal vectors, which eliminates harmonics in phase voltage without using a passive LC filtering technique. The power circuit topology uses a single dc-link supply for the primary inverter. The secondary inverter is fed with a capacitive supply. A novel topology is proposed for the dense six-level secondary inverter. The lower order harmonics in phase voltage are suppressed using the secondary inverter, which acts like a switched-capacitive filter. This article also proposes a novel capacitor voltage-balancing scheme for the first time, which achieves voltage balancing for secondary inverter capacitors. The voltages of secondary inverter capacitors are balanced using the power balance relationship between the primary inverter and the motor load. An experimental study of the topology and the capacitor-balancing scheme is presented for the validation of proposed scheme. |
